Under specialized cases, rather than globally thinning a semiconductor substrate it is desirable to thin an isolated defined area of the semiconductor substrate. Some cases where this technique might be applied:
 
  • Thinning large semiconductor substrates introduces the potential for release excessive compressive or tinsel mechanical stress across the die. When compressive or tinsel stresses exceed the limits of the die and microelectronic packaging die cracks and breaks at die-to-package interfaces may precipitate. Thinning isolated areas of large die where cracking and/or substrate stress is a concern. By thinning a small area of the die, the unthinnned areas of the die provide the mechanical support to mitigate cracking and maintain manageable stress across the area of the die.
 
  • When running wafer level fault isolation, it’s not feasible or necessary to thin the entire area of the wafer to successfully run fault isolation. Select area thinning allows our analysts for thin isolated areas of a wafer while preserving and maintaining the overall wafer.
 
  • With the increasing density of integrate circuits (ICs) topside focused ion beam (FIB) circuit edits (FIB-CE) are becoming more challenging and in many cases beyond the capabilities of the circuit edit tools available to industry today. Combining select area die thinning with a FIB extends the effectiveness and applicability of FIB for FIB-CE. In this application, the die is thinned in a defined area to a thickness which permits FIB-CE to be performed through the backside of the semiconductor substrate, effectively by-passing the obstructive metal routing.
 
 
The Ultra Tec ASAP-1 is the system we use to perform select area die/wafer thinning. Using a series of specialized polishing bits we slurries in conjunction with the ASAP-1 makes this process reliable, repeatable, and reproducible.